The present invention is directed to a method of operating a video game and more specifically to a method having a particular memory architecture using a microprocessor unit (MPU).
One type of video game uses what is termed a full memory map where in a random access memory there is a storage location or element for every possible resolution element on the video display screen. Thus a typical memory of this type might contain 61,240 bits to provide a 256.times.240 matrix of resolution elements. Such a memory map technique usually uses direct memory access (DMA) for the RAM memory which as defined in the "Microcomputer Dictionary and Guide" by Sippl and Kidd, First Edition 1976, published by Matrix Publishers of Champaign, Ill., as a procedure or method designed to gain direct access to main storage to thereby achieve data transfer without involving the CPU. However, the CPU must be periodically disabled while DMA is in progress thus reducing throughput. In other words, a cycle steal is occurring inhibiting the CPU operation during the direct memory access. In summary, the cycle steal DMA slows the program greatly. There must be many RAM accesses to refresh the cathode ray tube or display screen of the video game. Cycle steal is, of course, usually accomplished by the use of a "halt" input which halts microprocessor access.
One technique of remedying some of the above throughput disadvantages is shown by the prior art of FIG. 1 where instead of a full screen memory map a graphics programmable read only memory (PROM) 10 contains video data which will form the playfield of the video game which is read out on the line 11 which is connected to the video circuits. Addressing this graphics PROM is a playfield random access memory 12 which is in essence an address register for addressing the proper portion of the graphics PROM. This is controlled by an address bus 13 which is connected to RAM 12 by a multiplexer 14. Although the circuit of FIG. 1 provides improved throughput for the microprocessor unit it also requires separate motion circuits 16 to provide the moving portions of the video game.
Furthermore, in conjunction with FIG. 1 although the circuit is the type of direct memory access where in one phase of the access cycle the RAM 12 is addressed and next the data is read out of the PROM under the control of the sync allowing the microprocessor to perform other functions, the circuit of FIG. 1 still requires the separate graphics PROM and motion circuits in addition to the playfield RAM 12.